Basic Knowledge about Pipeline
Pipeline Phase
Some abbreviations: + IF: instruction fetch + D/RF: decode & register fetch phase + EX: execute phase + MEM: memory phase + WB: write-back phase
An Ideal Pipeline + Same process: all objects go through the same stages. + No shared resource: no sharing of resources between any two stages. + Equal propagation delay: propagation delay through all pipeline stages is equal. + No interplay: scheduling of a transaction entering the pipeline is not affected by the transactions in other stages.
Pipeline Graph
Always Remember, computer architecture is always a tradeoff philosophy.
Data Hazard
- Read-after-Write(RAW) hazard: Most common in basic pipeline method.
- Write-after-Read(WAR) hazard:
- Write-after-Write(WAW) hazard
Control Hazard
For MIPS, the branch condition cann't get its results until execute stage: If the branch is taken, we need to: + kill the two following instructions. + the instruction at the decode stage is invalid. For control hazard, the instruction right after the branch instruction need to kill its self.
How to reduce branch penalty? 1. One pipeline bubble can be removed if an extra comparator is used in the decode stage of the branch instruction, its disadvantage, however, is that it might elongate cycle time.[Resolve in decode stage] 2. Change the ISA semantics so that the instruction that the instruction that follows a jump or branch is always excuted, in other words, give the compiler the flexibility to put in a useful instruction where normally a pipeline buble would have resulted. [Branch Delay Slots]
Why an instruction may not be dispatched every clcle(CPI>1)? 1. Full bypassing may be too expensive to implement. + Typically all frequent used paths are provided. + However, some infrequently used bypass paths may increase cycle time and couteract the benefit of reducing CPI 2. Load instruction have at least one cycle latency. 3. Conditional branches may cause bubbles.