Superscalar

Interrupts

1. The definition of interrupts: An external or internal event that needs to be processed by another program. The event is usually unexpected or rare from program's point of view.
2. Cause of Exceptions

• Asynchronous: an external event
• input/output device service request
• timer expiration
• power disruptions, hardware failure
• Synchronous: an internal exception
• undefined opcode, privileged instruction
• arithmetic overflow, FPU exception
• misaligned memory access
• virtual memory exceptions: page fault
• software exceptions

3. When the processor decide to process the interrupt
   • It stops the current program at instruction \(l_i\), completes all the instructions up to \(l_{i-1}\), which is know as precise interrupt.
   • It saves the PC(program counter) of instruction \(l_i\) is a special register, which is known as EPC.
   • It disables interrupt and gives the control right to a designed interrupt handler running in the kernal mode.

Exception Handling

1. How to handle multiple simultaneous exceptions in different pipeline stages?

Let the oldest instruction that cause an exception kill all instruction behind in the pipeline.

2. How and where to handle external asynchronous interrupts?

See the reference: 1. 《Computer Architecture: A Quantitive Approach》: Chapter 3: Instruction-Level Parallelism and Its Exploitation 2. Coursera: David

Speculation and Branches

Register Renaming Introduction

WAW and WAR "Name" Dependencies

1. WAW and WAR are not True data dependencies.
2. RAW is True data dependency because reader needs results of writer.
3. Name dependencies exist because we have limited number of Names(register specifiers or memory addresses)

Question: What problems exist with adding infinite numbers of registers to a computer instruction set architecture? A. It takes huge area in the circuit to store these register values B. Takes up encoding space and encoding space is limited. C. It is difficult to manage infinite registers. D. There is no problem at all.

The right answer is B. Infinite numbers of registers will take up too much encoding space. * Adding more Names(registers/memory) removes dependence, but architecture namespace is limited. (32 registers requires 5 bits, 128 register require 7bits)

So, simplify increasing number of registers can not solve the problems.

Register Renaming

Register renaming means change naming of register in hardware to eliminate WAW and WAR hazards.

There are mainly two schemes of register renaming 1. Add pointers in the instruction Queue/ReOrder Buffer. 2. Store values in the instruction Queue/ReOrder Buffer.

See the reference: 1. 《Computer Architecture: A Quantitive Approach》: Chapter 3: Instruction-Level Parallelism and Its Exploitation 2. Coursera: David

Speculation and Branches

Register Renaming Introduction

WAW and WAR "Name" Dependencies

1. WAW and WAR are not True data dependencies.
2. RAW is True data dependency because reader needs results of writer.
3. Name dependencies exist because we have limited number of Names(register specifiers or memory addresses)

Question: What problems exist with adding infinite numbers of registers to a computer instruction set architecture? A. It takes huge area in the circuit to store these register values B. Takes up encoding space and encoding space is limited. C. It is difficult to manage infinite registers. D. There is no problem at all.

The right answer is B. Infinite numbers of registers will take up too much encoding space. * Adding more Names(registers/memory) removes dependence, but architecture namespace is limited. (32 registers requires 5 bits, 128 register require 7bits)

So, simplify increasing number of registers can not solve the problems.

Register Renaming

Register renaming means change naming of register in hardware to eliminate WAW and WAR hazards.

There are mainly two schemes of register renaming 1. Add pointers in the instruction Queue/ReOrder Buffer. 2. Store values in the instruction Queue/ReOrder Buffer.